[01] Umakanta Nanda, Department of Electronics and Communication Engineering, National Institute of Technology, Rourkela, India. [02] Debasish Nayak, Department of Electronics and Communication Engineering, National Institute of Technology, Rourkela, India.

A new very high performance low voltage cascode current mirror (CM) circuit is proposed in this work. The CM utilizes the low supply voltage and low input resistance characteristics of a cascode CM. In this CM, cascode configuration is used to obtain a wide operating current range and resistance compensation technique is incorporated to increase the operating bandwidth. The peaking in frequency response is reduced by use of an additional large MOSFET. The proposed CM is simulated by Cadence Analog Design Environment using UMC 90 nm CMOS technology. In the proposed CM a bandwidth of 570 MHz, the 1% settling time of 20 ns, input and output resistances of 25.41 Ω and 770.2 MΩ respectively are obtained with a single supply voltage of 1V.

Cascode Current Mirror, Low Supply Voltage, Passive and Active Resistors, Input Output Resistance and Bandwidth

[01] J Ramirez-Angulo , RG Carvajal , A. Torralba , "Low supply voltage high-performance CMOS current mirror with low input and output voltage requirements," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 51, pp. 124-129, 2004. [02] S Sharma , SS Rajput , LK Magotra , SS Jamuar, "FGMOS based wide range low," in Asia-Pacific Conference on Circuits and Systems, 2002. [03] VI Prodanov, MM Green, "CMOS current mirrors with reduced input and output voltage requirements," Electronics letters, vol. 32, pp. 104-105, 1996. [04] J Mulder , AC Van Ver Woerd, WA Serdijn , AHM Van Roermund , "High swing cascode MOS current mirror," Electronics letters, vol. 32, pp. 1251-1252, 1996. [05] H Chen, KN. Leung, "A Fast-Transient LDO Based on Buffered Flipped Voltage follower," in IEEE International Conference on Electron Devices and Solid-State circuits, China, 2010. [06] Philip E Allen, Douglus R Holburg, CMOS Analog Circuit Design, 2nd Edition, Oxford University Press, 2000. [07] R. J. Baker, H. W. Li and D. E. Boyce, “CMOS Circuit Design, Layout, and Simulation,” IEEE Press Series on Microelectronic Systems, 2002. [08] M.-H.Cheng, Z.-W. Wu, "Low-power low-voltage reference using peaking current mirror circuit," Electronics Letters, vol.41, no.10, pp.572-573, 12 May 2005.