Physics Journal
Articles Information
Physics Journal, Vol.1, No.3, Nov. 2015, Pub. Date: Nov. 12, 2015
Analytical Investigation of Triple-Material Cylindrical Gate-Surrounded (TM-CGS) MOSFETs with High-KMaterial Oxide
Pages: 325-330 Views: 1617 Downloads: 1074
Authors
[01] M. Jouri, Faculty of Electrical and Computer Engineering, Hakim Sabzevari University, Sabzevar, Iran.
[02] M. H. Shahrokh Abadi, Faculty of Electrical and Computer Engineering, Hakim Sabzevari University, Sabzevar, Iran.
Abstract
An analytical model for the short channel cylindrical / surrounding gate MOSFET based on the solution of Poisson’s Equation in the parabolic approximation of the potential along the radial axis is presented in this work. Three different electrodes, having different work-functions, and three different high-k dielectric materials have been used as thegate contacts and the gate oxides, respectively, to prevent direct tunneling leakage current in the device. The center and the surface potential models have been obtained by solving the 2-D Poisson’s equation in the cylindrical coordinate system. The effects of physical parameters such as cylinder diameter, oxide thickness, gate length ratio, natural length of the center potential, and sub-threshold swing have been investigated in the device by using MATLAB simulator. The results show that introducing triple high-k material can modify the impact of drain-induced barrier lowering, DIBL. A significant decrease in the center potential due to applying different gate oxides has been observed and compared to those with single oxide film.For further verification of the results, a calibrationapproach for the device performance has been also taken into account.
Keywords
MOSFET, Gate Surrounded, Poisson’s Equation, Short Channel Effect, Drain Induced Barrier Lowering, Subthreshold Swing
References
[01] Kranti, A., Haldar, S., Gupta, R.S.(2001). An accurate 2D analytical model for short channel thin film fully depleted cylindrical/surrounding gate (CGT/SGT) MOSFET. Elsevier. Microelectronics Journal. 32: 305-313.
[02] Kranti, A.,Haldar, S., Gupta, R.S.(2001). Analytical model for threshold voltage and I–V characteristics of fully depleted short channel cylindrical / surrounding gate MOSFET. Elsevier. Microelectronics Journal. 56: 241–259.
[03] Dubey, S., Santra, A., Saramekala, G., Kumar, M., and Tiwari, P.K.(2013). An Analytical Threshold Voltage Model for Triple-Material Cylindrical Gate-All-Around (TM-CGAA) MOSFETs. IEEE Trans. Nanotechnology. 12(5): 766-774.
[04] Sang-Hyun Oh, Don Monroe, Hergenrother J.M.(2000) Analytic Description of Short-Channel Effects in Fully-Depleted Double-Gate and Cylindrical, Surrounding-Gate MOSFETs. IEEE Trans. Electron Devices. 21(9): 445-447.
[05] Gupta, S.K., Baishya, S. (2012). Modeling and Simulation of Triple Metal Cylindrical Surround Gate MOSFETs for Reduced Short Channel Effects. International Journal of Soft Computing and Engineering (IJSCE). 2(2): 214-221.
[06] Ghosh, P., Haldar, S., Gupta, R.S., Gupta, M. (2012). Analytical Modeling and Simulation for Dual Metal Gate Stack Architecture (DMGSA) Cylindrical/Surrounded Gate MOSFET. Journal of Semiconductor Technology and Science. 12(4): 458-466.
[07] Kumar, M., Haldar, S., Gupta, M., Gupta, R.S. (2014). Impact of gate material engineering (GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless applications: 3D T-CAD simulation. Elsevier. MicroelectronicsJournal 45: 1508-1514.
[08] Pradhan, K.P., Mohapatra, S.K., Sahu, P.K., Behera, D.K. (2014). Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET. Elsevier. MicroelectronicsJournal 45: 144-151.
[09] Sharma, R.K., Gupta, M., Gupta, R.S. (2011). TCAD Assessment of Device Design Technologies for Enhanced Performance of Nanoscale DG MOSFET. IEEE Trans. Electron Devices. 58(9): 245-251.
[10] Marin, E.G., Ruiz, F.G., Tienda-Luna, I.M., Godoy, A., Sánchez-Moreno, P. (2012). Analytic potential and charge model for III-V surrounding gate metal-oxide semiconductor field-effect transistors. J. Appl. Phys. 112: 29905-29911,doi: 10.1063/1.4759275.
[11] Yun Seop Yu, Namki Cho, Sung Woo Hwang, and DoyeolAhn. (2010). Analytical Threshold Voltage Model Including Effective Conducting Path Effect (ECPE) for Surrounding-Gate MOSFETs (SGMOSFETs) With Localized Charges. IEEE trans. electron devices.57(11): 3176-3180.
[12] Te-Kuang, C. (2010). A Compact Analytical Threshold-Voltage Model for Surrounding-Gate MOSFETs With Interface Trapped Charges. IEEE Electron Device Letters. 31(8): 788-790.
[13] Song, J. Y., Choi, W.Y., Park, J.H., Lee, J. D., Park, B. G. (2006). Design Optimization of Gate-All-Around (GAA) MOSFETs. IEEE Trans. Nanotechnology. 5(3):186-191.
[14] Gautam, R., Saxena, M., Gupta, R.S., Gupta, M. (2013). Hot-Carrier Reliability of Gate-All-Around MOSFET for RF/Microwave Applications. IEEE Trans. Device and Materials Reliability. 13(1): 245-251.
[15] Pratap, Y., Ghosh, P., Haldar, S., Gupta, R.S., Gupta, M. (2014). An analytical subthreshold current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of device design engineering. Elsevier. Microelectronics Journal 45: 408–415.
[16] Sharma, S. and Kumar, P. (2008). Optimizing Effective Channel Length to Minimize Short Channel Effects in Sub-50 nm Single/Double Gate SOI MOSFETs. JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE. 8(2): 170-177.
600 ATLANTIC AVE, BOSTON,
MA 02210, USA
+001-6179630233
AIS is an academia-oriented and non-commercial institute aiming at providing users with a way to quickly and easily get the academic and scientific information.
Copyright © 2014 - American Institute of Science except certain content provided by third parties.